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CODES
2004
IEEE
14 years 2 months ago
Operation tables for scheduling in the presence of incomplete bypassing
Register bypassing is a powerful and widely used feature in modern processors to eliminate certain data hazards. Although complete bypassing is ideal for performance, bypassing ha...
Aviral Shrivastava, Eugene Earlie, Nikil D. Dutt, ...
COOPIS
2004
IEEE
14 years 2 months ago
A Distributed and Parallel Component Architecture for Stream-Oriented Applications
Abstract. This paper introduces ThreadMill - a distributed and parallel component architecture for applications that process large volumes of streamed (time-sequenced) data, such a...
Paulo Barthelmess, Clarence A. Ellis
CASES
2006
ACM
14 years 2 months ago
Reaching fast code faster: using modeling for efficient software thread integration on a VLIW DSP
When integrating software threads together to boost performance on a processor with instruction-level parallel processing support, it is rarely clear which code regions should be ...
Won So, Alexander G. Dean
FPGA
2004
ACM
140views FPGA» more  FPGA 2004»
14 years 2 months ago
Using reconfigurability to achieve real-time profiling for hardware/software codesign
Embedded systems combine a processor with dedicated logic to meet design specifications at a reasonable cost. The attempt to amalgamate two distinct design environments introduces...
Lesley Shannon, Paul Chow
ICS
2010
Tsinghua U.
14 years 11 days ago
Timing local streams: improving timeliness in data prefetching
Data prefetching technique is widely used to bridge the growing performance gap between processor and memory. Numerous prefetching techniques have been proposed to exploit data pa...
Huaiyu Zhu, Yong Chen, Xian-He Sun