115 search results - page 19 / 23 » Sequential Circuit Verification Using Symbolic Model Checkin... |
ASPDAC
2005
ACM
13 years 9 months ago
2005
ACM
- We address the problem of implication of assertion graphs that occur in generalized symbolic trajectory evaluation (GSTE). GSTE has demonstrated its powerful capacity in formal v...
ICCAD
2002
IEEE
14 years 4 months ago
2002
IEEE
In this survey, we outline basic SAT- and ATPGprocedures as well as their applications in formal hardware verification. We attempt to give the reader a trace trough literature and...
ASPDAC
2006
ACM
14 years 1 months ago
2006
ACM
— Process variations in digital circuits make sequential circuit timing validation an extremely challenging task. In this paper, a Statistical Bellman-Ford (SBF) algorithm is pro...
ISSTA
2010
ACM
13 years 9 months ago
2010
ACM
SAT-based bounded verification of annotated code consists of translating the code together with the annotations to a propositional formula, and analyzing the formula for specifica...
ESOP
2008
Springer
13 years 9 months ago
2008
Springer
Abstract. We survey recent developments in an approach to the verification of higher-order computation based on game semantics. Higherorder recursion schemes are in essence (progra...