115 search results - page 8 / 23 » Sequential Circuit Verification Using Symbolic Model Checkin... |
TACAS
1998
Springer
13 years 11 months ago
1998
Springer
A state/event model is a concurrent version of Mealy machines used for describing embedded reactive systems. This paper introduces a technique that uses compositionality and depend...
ICSE
2007
IEEE-ACM
14 years 7 months ago
2007
IEEE-ACM
The Alloy tool-set has been gaining popularity as an alternative to traditional manual testing and checking for design correctness. Alloy uses a first-order relational logic for m...
ARTS
1999
Springer
13 years 12 months ago
1999
Springer
Model checking can tell us whether a system is correct; probabilistic model checking can also tell us whether a system is timely and reliable. Moreover, probabilistic model checkin...
KBSE
2007
IEEE
14 years 1 months ago
2007
IEEE
A number of researchers have proposed the use of Boolean satisfiability solvers for verifying C programs. They encode correctness checks as Boolean formulas using finitization: ...
ISQED
2003
IEEE
14 years 26 days ago
2003
IEEE
This paper describes the use of integer equations for high level modeling digital circuits for application of formal verification properties at this level. Most formal verificatio...