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IAJIT
2010
84views more  IAJIT 2010»
13 years 6 months ago
A Test Procedure for Boundary Scan Circuitry in PLDs and FPGAs
: A test procedure for testing mainly the boundary scan cells, and testing partially the test access port controller in programmable logic devices, and field programmable gate arra...
Bashar Al-Khalifa
TCAD
2008
114views more  TCAD 2008»
13 years 7 months ago
Test-Quality/Cost Optimization Using Output-Deviation-Based Reordering of Test Patterns
At-speed functional testing, delay testing, and n-detection test sets are being used today to detect deep submicrometer defects. However, the resulting test data volumes are too hi...
Zhanglei Wang, Krishnendu Chakrabarty
FDTC
2006
Springer
106views Cryptology» more  FDTC 2006»
13 years 11 months ago
Sign Change Fault Attacks on Elliptic Curve Cryptosystems
We present a new type of fault attacks on elliptic curve scalar multiplications: Sign Change Attacks. These attacks exploit different number representations as they are often emplo...
Johannes Blömer, Martin Otto 0002, Jean-Pierr...
EUROGP
2009
Springer
105views Optimization» more  EUROGP 2009»
14 years 2 days ago
Quantum Circuit Synthesis with Adaptive Parameters Control
The contribution presented herein proposes an adaptive genetic algorithm applied to quantum logic circuit synthesis that, dynamically adjusts its control parameters. The adaptation...
Cristian Ruican, Mihai Udrescu, Lucian Prodan, Mir...
EUC
2007
Springer
13 years 11 months ago
The Reliability of Detection in Wireless Sensor Networks: Modeling and Analyzing
A Wireless Sensor Network (WSN) composed of tiny sensor nodes may operate in an unfavorable terrain. The coupling of inherent limitations and harsh environments makes WSNs fallible...
Ming-Tsung Hsu, Frank Yeong-Sung Lin, Yue-Shan Cha...