1053 search results - page 79 / 211 » Shape as Memory Storage |
AINA
2007
IEEE
14 years 4 months ago
2007
IEEE
The widening gap between CPU and memory speed has made caches an integral feature of modern highperformance processors. The high degree of configurability of cache memory can requ...
ETS
2007
IEEE
14 years 4 months ago
2007
IEEE
An efficient on-chip infrastructure for memory test and repair is crucial to enhance yield and availability of SoCs. Therefore embedded memories are commonly equipped with spare r...
EP
1998
Springer
14 years 2 months ago
1998
Springer
Abstract. Multimedia style sheet systems uniformly use a constraintbased model of layout. Constraints provide a uniform mechanism for all aspects of style management and layout and...
ISCAS
1994
IEEE
14 years 2 months ago
1994
IEEE
This paper presents a novel VLSI architecture for high-speed data compressor designs which implement the well-known LZ77 algorithm. The architecture mainly consists of three units...
CASES
2010
ACM
13 years 8 months ago
2010
ACM
We present a fine-grain dynamic instruction placement algorithm for small L0 scratch-pad memories (spms), whose unit of transfer can be an individual instruction. Our algorithm ca...