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ICCAD
2002
IEEE
80views Hardware» more  ICCAD 2002»
14 years 4 months ago
Minimizing power across multiple technology and design levels
Approaches to achieve low-power and high-speed VLSI's are described with the emphasis on techniques across multiple technology and design levels. To suppress the leakage curr...
Takayasu Sakurai
FGCS
2006
83views more  FGCS 2006»
13 years 7 months ago
Memory-efficient Kronecker algorithms with applications to the modelling of parallel systems
We present a new algorithm for computing the solution of large Markov chain models whose generators can be represented in the form of a generalized tensor algebra, such as network...
Anne Benoit, Brigitte Plateau, William J. Stewart
CGO
2011
IEEE
12 years 11 months ago
Practical memory checking with Dr. Memory
—Memory corruption, reading uninitialized memory, using freed memory, and other memory-related errors are among the most difficult programming bugs to identify and fix due to t...
Derek Bruening, Qin Zhao
EVOW
2011
Springer
12 years 11 months ago
Two Iterative Metaheuristic Approaches to Dynamic Memory Allocation for Embedded Systems
Abstract. Electronic embedded systems designers aim at finding a tradeoff between cost and power consumption. As cache memory management has been shown to have a significant imp...
María Soto, André Rossi, Marc Sevaux
ASPDAC
2012
ACM
253views Hardware» more  ASPDAC 2012»
12 years 3 months ago
An integrated and automated memory optimization flow for FPGA behavioral synthesis
Behavioral synthesis tools have made significant progress in compiling high-level programs into register-transfer level (RTL) specifications. But manually rewriting code is still ...
Yuxin Wang, Peng Zhang, Xu Cheng, Jason Cong