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CHES
2008
Springer
146views Cryptology» more  CHES 2008»
13 years 10 months ago
Power and Fault Analysis Resistance in Hardware through Dynamic Reconfiguration
Dynamically reconfigurable systems are known to have many advantages such as area and power reduction. The drawbacks of these systems are the reconfiguration delay and the overhead...
Nele Mentens, Benedikt Gierlichs, Ingrid Verbauwhe...
ICECCS
2009
IEEE
161views Hardware» more  ICECCS 2009»
14 years 3 months ago
Formal Modelling and Analysis of Business Information Applications with Fault Tolerant Middleware
Distributed information systems are critical to the functioning of many businesses; designing them to be dependable is a challenging but important task. We report our experience i...
Jeremy Bryans, John S. Fitzgerald, Alexander Roman...
DSD
2005
IEEE
106views Hardware» more  DSD 2005»
14 years 2 months ago
SystemC-based Design Methodology for Reconfigurable System-on-Chip
Reconfigurable system is a promising alternative to deliver both flexibility and performance at the same time. New reconfigurable technologies and technologydependent tools have b...
Yang Qu, Kari Tiensyrjä, Juha-Pekka Soininen
CODES
2006
IEEE
14 years 2 months ago
TLM/network design space exploration for networked embedded systems
This paper presents a methodology to combine Transaction Level Modeling and System/Network co-simulation for the design of networked embedded systems. As a result, a new design di...
Nicola Bombieri, Franco Fummi, Davide Quaglia
CASES
2004
ACM
14 years 2 months ago
High-level power analysis for on-chip networks
As on-chip networks become prevalent in multiprocessor systemson-a-chip and multi-core processors, they will be an integral part of the design flow of such systems. With power in...
Noel Eisley, Li-Shiuan Peh