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» Simulation Model Verification and Validation: Increasing the...
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DAC
2006
ACM
14 years 8 months ago
Formal analysis of hardware requirements
Formal languages are increasingly used to describe the functional requirements (specifications) of circuits. These requirements are used as a means to communicate design intent an...
Ingo Pill, Simone Semprini, Roberto Cavada, Marco ...
SIGSOFT
2001
ACM
14 years 8 months ago
Detecting implied scenarios in message sequence chart specifications
Scenario-based specifications such as Message Sequence Charts (MSCs) are becoming increasingly popular as part of a requirements specification. Scenarios describe how system compo...
Jeff Kramer, Jeff Magee, Sebastián Uchitel
JCP
2006
116views more  JCP 2006»
13 years 7 months ago
Building a Virtual Hierarchy for Managing Trust Relationships in a Hybrid Architecture
Trust models provide a framework to create and manage trust relationships among the different entities of a Public Key Infrastructure (PKI). These trust relationships are verified ...
Cristina Satizábal, Rafael Páez, Jor...
EMSOFT
2008
Springer
13 years 9 months ago
Automatically transforming and relating Uppaal models of embedded systems
Relations between models are important for effective automatic validation, for comparing implementations with specifications, and for increased understanding of embedded systems d...
Timothy Bourke, Arcot Sowmya
CSE
2009
IEEE
14 years 2 months ago
Social Inference Risk Modeling in Mobile and Social Applications
— The emphasis of emerging mobile and Web 2.0 applications on collaboration and communication increases threats to user privacy. A serious, yet under-researched privacy risk resu...
Sara Motahari, Sotirios G. Ziavras, Mor Naaman, Mo...