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FCCM
2006
IEEE
133views VLSI» more  FCCM 2006»
14 years 5 months ago
A Scalable FPGA-based Multiprocessor
It has been shown that a small number of FPGAs can significantly accelerate certain computing tasks by up to two or three orders of magnitude. However, particularly intensive lar...
Arun Patel, Christopher A. Madill, Manuel Salda&nt...
ISCA
2012
IEEE
232views Hardware» more  ISCA 2012»
12 years 1 months ago
RADISH: Always-on sound and complete race detection in software and hardware
Data-race freedom is a valuable safety property for multithreaded programs that helps with catching bugs, simplifying memory consistency model semantics, and verifying and enforci...
Joseph Devietti, Benjamin P. Wood, Karin Strauss, ...
VLSID
2005
IEEE
167views VLSI» more  VLSID 2005»
14 years 11 months ago
A Methodology and Tooling Enabling Application Specific Processor Design
This paper presents a highly efficient processor design methodology based on the LISA 2.0 language. Typically the architecture design phase is dominated by an iterative processor ...
Andreas Hoffmann, Frank Fiedler, Achim Nohl, Suren...
ICDE
2009
IEEE
126views Database» more  ICDE 2009»
14 years 5 months ago
Instant Advertising in Mobile Peer-to-Peer Networks
— To explore the benefit of advertising instant and location-aware commercials that can not be effectively promoted by traditional medium like TV program and Internet, we propos...
Zaiben Chen, Heng Tao Shen, Quanqing Xu, Xiaofang ...
ICC
2009
IEEE
190views Communications» more  ICC 2009»
14 years 5 months ago
Decomposition for Low-Complexity Near-Optimal Routing in Multi-Hop Wireless Networks
Abstract—Network flow models serve as a popular mathematical framework for the analysis and optimization of Multi-hop Wireless Networks. They also serve to provide the understan...
Vinay Kolar, Nael B. Abu-Ghazaleh, Petri Mäh&...