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» Simulation Modeling at Multiple Levels of Abstraction
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ASPDAC
2006
ACM
133views Hardware» more  ASPDAC 2006»
14 years 1 months ago
An SPU reference model for simulation, random test generation and verification
– An instruction set level reference model was developed for the development of synergistic processing unit (SPU) , which is one of the key components of the cell processor [1][2...
Yukio Watanabe, Balazs Sallay, Brad W. Michael, Da...
PADS
2004
ACM
14 years 25 days ago
The Effect of Detail on Ethernet Simulation
An important question for network simulation is what level of detail is required to obtain a desired level of accuracy. While in some networks, the level of detail is an open rese...
Alefiya Hussain, Aman Kapoor, John S. Heidemann
QEST
2009
IEEE
14 years 2 months ago
Language-Level Symmetry Reduction for Probabilistic Model Checking
—Symmetry reduction is a technique for combating state-space explosion in model checking. The generic representatives approach to symmetry reduction uses a language-level transla...
Alastair F. Donaldson, Alice Miller, David Parker
DATE
2008
IEEE
86views Hardware» more  DATE 2008»
14 years 1 months ago
Test Scheduling for Wafer-Level Test-During-Burn-In of Core-Based SoCs
Abstract—Wafer-level test during burn-in (WLTBI) has recently emerged as a promising technique to reduce test and burn-in costs in semiconductor manufacturing. However, the testi...
Sudarshan Bahukudumbi, Krishnendu Chakrabarty, Ric...
MODELS
2009
Springer
14 years 1 months ago
HiLA: High-Level Aspects for UML State Machines
UML state machines are widely used for modeling software behavior. However state-crosscutting behaviors, such as synchronization or execution history dependence, are hard to model...
Gefei Zhang, Matthias M. Hölzl