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ICCD
2004
IEEE
129views Hardware» more  ICCD 2004»
14 years 4 months ago
Cache Array Architecture Optimization at Deep Submicron Technologies
A cache access time model, PRACTICS (PRedictor of Access and Cycle TIme for Cache Stack), has been developed to optimize the memory array architecture for the minimum access and c...
Annie (Yujuan) Zeng, Kenneth Rose, Ronald J. Gutma...
VLSID
2002
IEEE
116views VLSI» more  VLSID 2002»
14 years 8 months ago
Efficient Macromodeling for On-Chip Interconnects
The improved T and improved n models are proposed for onchip interconnect macromodeling. Using global approximations, simple approximation frames are derived and applied to modeli...
Qinwei Xu, Pinaki Mazumder
ICC
2000
IEEE
241views Communications» more  ICC 2000»
14 years 8 days ago
Power Management for Throughput Enhancement in Wireless Ad-Hoc Networks
—In this paper we introduce the notion of power management within the context of wireless ad-hoc networks. More specifically, we investigate the effects of using different trans...
Tamer A. ElBatt, Srikanth V. Krishnamurthy, Dennis...
CORR
2007
Springer
117views Education» more  CORR 2007»
13 years 7 months ago
Sensor Networks with Random Links: Topology Design for Distributed Consensus
—In a sensor network, in practice, the communication among sensors is subject to: 1) errors that can cause failures of links among sensors at random times; 2) costs; and 3) const...
Soummya Kar, José M. F. Moura
GLVLSI
2005
IEEE
67views VLSI» more  GLVLSI 2005»
14 years 1 months ago
Energy recovery clocked dynamic logic
Energy recovery clocking results in significant energy savings in clock distribution networks as compared to conventional squarewave clocking. However, since energy recovery clock...
Matthew Cooke, Hamid Mahmoodi-Meimand, Qikai Chen,...