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MICRO
2010
IEEE
202views Hardware» more  MICRO 2010»
13 years 3 months ago
Hardware Support for Relaxed Concurrency Control in Transactional Memory
Today's transactional memory systems implement the two-phase-locking (2PL) algorithm which aborts transactions every time a conflict happens. 2PL is a simple algorithm that pr...
Utku Aydonat, Tarek S. Abdelrahman
CASES
2008
ACM
13 years 11 months ago
Efficiency and scalability of barrier synchronization on NoC based many-core architectures
Interconnects based on Networks-on-Chip are an appealing solution to address future microprocessor designs where, very likely, hundreds of cores will be connected on a single chip...
Oreste Villa, Gianluca Palermo, Cristina Silvano
BMCBI
2007
102views more  BMCBI 2007»
13 years 9 months ago
Setting up a large set of protein-ligand PDB complexes for the development and validation of knowledge-based docking algorithms
Background: The number of algorithms available to predict ligand-protein interactions is large and ever-increasing. The number of test cases used to validate these methods is usua...
Luis A. Diago, Persy Morell, Longendri Aguilera, E...
SIGIR
2003
ACM
14 years 2 months ago
HAT: a hardware assisted TOP-DOC inverted index component
A novel Hardware Assisted Top-Doc (HAT) component is disclosed. HAT is an optimized content indexing device based on a modified inverted index structure. HAT accommodates patterns...
S. Kagan Agun, Ophir Frieder
SP
2002
IEEE
109views Security Privacy» more  SP 2002»
13 years 8 months ago
Scalable atomistic simulation algorithms for materials research
A suite of scalable atomistic simulation programs has been developed for materials research based on space-time multiresolution algorithms. Design and analysis of parallel algorit...
Aiichiro Nakano, Rajiv K. Kalia, Priya Vashishta, ...