105 search results - page 12 / 21 » Simulation based architectural power estimation for PLA-base... |
NOCS
2007
IEEE
14 years 2 months ago
2007
IEEE
The paper introduces Network-on-Chip (NoC) design methodology and low cost mechanisms for supporting efficient cache access and cache coherency in future high-performance Chip Mul...
GLOBECOM
2007
IEEE
14 years 2 months ago
2007
IEEE
This paper addresses initial ranging (uplink synchronization and power control) for TDD OFDMA systems. Exploiting the channel knowledge from the downlink channel together with ini...
HIPEAC
2005
Springer
14 years 2 months ago
2005
Springer
Abstract. Power efficiency has become a key design trade-off in embedded system designs. For system-on-a-chip embedded systems, an external bus interconnects embedded processor co...
DSRT
2008
IEEE
14 years 3 months ago
2008
IEEE
According to statistics and future prospects in the next few years world-wide energy consumption will increase significantly. Therefore not only more energy efficient technologi...
ICCD
1999
IEEE
14 years 27 days ago
1999
IEEE
This paper describes a core-customization process of a CISC processor core for a given application program. It aims at the power reduction in the CISC processor core by fully util...