Sciweavers

943 search results - page 144 / 189
» Simulation based deadlock analysis for system level designs
Sort
View
DATE
2005
IEEE
164views Hardware» more  DATE 2005»
14 years 2 months ago
Automated Synthesis of Assertion Monitors using Visual Specifications
Automated synthesis of monitors from high-level properties plays a significant role in assertion-based verification. We present here a methodology to synthesize assertion monitors...
Ambar A. Gadkari, S. Ramesh
LREC
2008
80views Education» more  LREC 2008»
13 years 10 months ago
Phone Segmentation Tool with Integrated Pronunciation Lexicon and Czech Phonetically Labelled Reference Database
Phonetic segmentation is the procedure which is used in many applications of speech processing, both as a subpart of automated systems or as the tool for an interactive work. In t...
Petr Pollák, Jan Volín, Radek Skarni...
IASSE
2004
13 years 10 months ago
Execution of A Requirement Model in Software Development
Latest research results have shown that requirements errors have a prolonged impact on software development and that they are more expensive to fix during later stages than early ...
Wuwei Shen, Mohsen Guizani, Zijiang Yang, Kevin J....
BMCBI
2005
88views more  BMCBI 2005»
13 years 8 months ago
Using large-scale perturbations in gene network reconstruction
Background: Recent analysis of the yeast gene network shows that most genes have few inputs, indicating that enumerative gene reconstruction methods are both useful and computatio...
Thomas MacCarthy, Andrew Pomiankowski, Robert Seym...
ICST
2009
IEEE
13 years 6 months ago
Putting Formal Specifications under the Magnifying Glass: Model-based Testing for Validation
A software development process is conceptually an abstract form of model transformation, starting from an enduser model of requirements, through to a system model for which code c...
Emine G. Aydal, Richard F. Paige, Mark Utting, Jim...