943 search results - page 63 / 189 » Simulation based deadlock analysis for system level designs |
VALUETOOLS
2006
ACM
14 years 2 months ago
2006
ACM
Cache locality optimization is an efficient way for reducing the idle time of modern processors in waiting for needed data. This kind of optimization can be achieved either on the...
EURODAC
1994
IEEE
14 years 1 months ago
1994
IEEE
This paper presents a testability improvement method for digital systems described in VHDL behavioral specification. The method is based on testability analysis at registertransfe...
INFOCOM
2010
IEEE
13 years 7 months ago
2010
IEEE
— Internet traffic is expected to grow phenomenally over the next five to ten years, and to cope with such large traffic volumes, core networks are expected to scale to capaci...
GLVLSI
2008
IEEE
14 years 3 months ago
2008
IEEE
Due to the increasing complexity of today’s embedded systems, the analysis and validation of such systems is becoming a major challenge. UML is gradually adopted in the embedded...
GECCO
2008
Springer
2008
Springer
Bond-graphs + genetic programming: analysis of an automatically synthesized rotary mechanical system
13 years 10 months ago
Initial results of an experiment devised to combine Bond-Graph modeling and simulation with genetic programming for automated design of a simple mechatronic system are reported in...