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CASES
2008
ACM
13 years 10 months ago
Efficiency and scalability of barrier synchronization on NoC based many-core architectures
Interconnects based on Networks-on-Chip are an appealing solution to address future microprocessor designs where, very likely, hundreds of cores will be connected on a single chip...
Oreste Villa, Gianluca Palermo, Cristina Silvano
SIGCOMM
1998
ACM
14 years 28 days ago
Quality of Service Based Routing: A Performance Perspective
Recent studies provide evidence that Quality ofService QoS routing can provide increased network utilization compared to routing that is not sensitive to QoS requirements of tra...
George Apostolopoulos, Roch Guérin, Sanjay ...
ICS
2005
Tsinghua U.
14 years 2 months ago
Improved automatic testcase synthesis for performance model validation
Performance simulation tools must be validated during the design process as functional models and early hardware are developed, so that designers can be sure of the performance of...
Robert H. Bell Jr., Lizy Kurian John
DSD
2010
IEEE
144views Hardware» more  DSD 2010»
13 years 9 months ago
On-chip Scan-Based Test Strategy for a Dependable Many-Core Processor Using a NoC as a Test Access Mechanism
—Periodic on-chip scan-based tests have to be applied to a many-core processor SoC to improve its dependability. An infrastructural IP module has been designed and incorporated i...
Xiao Zhang, Hans G. Kerkhoff, Bart Vermeulen
GIS
2010
ACM
13 years 6 months ago
A data stream-based evaluation framework for traffic information systems
Traffic information systems based on mobile, in-car sensor technology are a challenge for data management systems as a huge amount of data has to be processed in real-time. Data m...
Sandra Geisler, Christoph Quix, Stefan Schiffer