—In this paper, we propose a high speed adder which is adopted for our reconfigurable architecture called FleXilicon. To support sub-word parallelism, the FleXilicon architecture...
This paper presents a fault tolerant design technique for the clockless wave pipeline. The specific architectural model investigated in this paper is the two-phase clockless asyn...
T. Feng, Byoungjae Jin, J. Wang, Nohpill Park, Yon...
We propose a new approach to easily creating 3 0 geometric models. A technique called interactive evolutionary computation (IEC) is introduced to accelerate user’s invention and...
In the nanometer manufacturing region, process variation causes significant uncertainty for circuit performance verification. Statistical static timing analysis (SSTA) is thus dev...
Increased complexity of simulation models and the related modeling needs for global supply chains have necessitated the execution of simulations on multiple processors. While dist...