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ISCAS
2007
IEEE
84views Hardware» more  ISCAS 2007»
14 years 3 months ago
High Speed 1-bit Bypass Adder Design for Low Precision Additions
—In this paper, we propose a high speed adder which is adopted for our reconfigurable architecture called FleXilicon. To support sub-word parallelism, the FleXilicon architecture...
Jong-Suk Lee, Dong Sam Ha
CF
2004
ACM
14 years 2 months ago
Fault tolerant clockless wave pipeline design
This paper presents a fault tolerant design technique for the clockless wave pipeline. The specific architectural model investigated in this paper is the two-phase clockless asyn...
T. Feng, Byoungjae Jin, J. Wang, Nohpill Park, Yon...
ICOIN
2001
Springer
14 years 1 months ago
A 3D Modeling System for Creative Design
We propose a new approach to easily creating 3 0 geometric models. A technique called interactive evolutionary computation (IEC) is introduced to accelerate user’s invention and...
Hiroaki Nishino, Hideyuki Takagi, Sung-Bae Cho, Ko...
ASPDAC
2008
ACM
200views Hardware» more  ASPDAC 2008»
13 years 11 months ago
Non-Gaussian statistical timing analysis using second-order polynomial fitting
In the nanometer manufacturing region, process variation causes significant uncertainty for circuit performance verification. Statistical static timing analysis (SSTA) is thus dev...
Lerong Cheng, Jinjun Xiong, Lei He
WSC
2004
13 years 10 months ago
A Framework for Adaptive Synchronization of Distributed Simulations
Increased complexity of simulation models and the related modeling needs for global supply chains have necessitated the execution of simulations on multiple processors. While dist...
Bertan Altuntas, Richard A. Wysk