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ARCS
2009
Springer
14 years 2 months ago
Improving Memory Subsystem Performance Using ViVA: Virtual Vector Architecture
The disparity between microprocessor clock frequencies and memory latency is a primary reason why many demanding applications run well below peak achievable performance. Software c...
Joseph Gebis, Leonid Oliker, John Shalf, Samuel Wi...
CODES
2008
IEEE
14 years 2 months ago
Static analysis of processor stall cycle aggregation
Processor Idle Cycle Aggregation (PICA) is a promising approach for low power execution of processors, in which small memory stalls are aggregated to create a large one, and the p...
Jongeun Lee, Aviral Shrivastava
CODES
2007
IEEE
14 years 2 months ago
HW/SW co-design for Esterel processing
We present a co-synthesis approach that accelerates reactive software processing by moving the calculation of complex expressions into external combinational hardware. The startin...
Sascha Gädtke, Claus Traulsen, Reinhard von H...
GECCO
2005
Springer
149views Optimization» more  GECCO 2005»
14 years 1 months ago
There's more to a model than code: understanding and formalizing in silico modeling experience
Mapping biology into computation has both a domain specific aspect – biological theory – and a methodological aspect – model development. Computational modelers have implici...
Janet Wiles, Nicholas Geard, James Watson, Kai Wil...
PROMISE
2010
13 years 2 months ago
Defect cost flow model: a Bayesian network for predicting defect correction effort
Background. Software defect prediction has been one of the central topics of software engineering. Predicted defect counts have been used mainly to assess software quality and est...
Thomas Schulz, Lukasz Radlinski, Thomas Gorges, Wo...