154 search results - page 6 / 31 » Simulation of Bulk Flow and High Speed Operations |
ASYNC
2003
IEEE
14 years 28 days ago
2003
IEEE
We present a high-speed, clockless, serial link transceiver for inter-chip communication in asynchronous VLSI systems. Serial link transceivers achieve high offchip data rates by ...
ARVLSI
1997
IEEE
13 years 12 months ago
1997
IEEE
This paper describes the architecture and implementation of a high-speed decompression engine for embedded processors. The engine is targeted to processors where embedded programs...
DAC
1996
ACM
13 years 11 months ago
1996
ACM
This paper presents the design of a Videophone CoderDecoder Motion Estimator using two High-Level Synthesis tools. Indeed, the combination of a Control Flow Dominated part (comple...
INFOCOM
2003
IEEE
14 years 28 days ago
2003
IEEE
Abstract—Link bundling is a way to increase routing scalability whenever a pair of Label Switching Routers in MPLS are connected by multiple parallel links. However, link bundlin...
GECCO
2008
Springer
13 years 8 months ago
2008
Springer
One of the major difficulties when applying Multiobjective Evolutionary Algorithms (MOEA) to real world problems is the large number of objective function evaluations. Approximate...