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» Simulation of High-Performance Memory Allocators
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ISCA
1991
IEEE
110views Hardware» more  ISCA 1991»
14 years 2 months ago
Dynamic Base Register Caching: A Technique for Reducing Address Bus Width
When address reference streams exhibit high degrees of spatial and temporal locality, many of the higher order address lines carry redundant information. By caching the higher ord...
Matthew K. Farrens, Arvin Park
SIGCOMM
2012
ACM
12 years 1 months ago
FairCloud: sharing the network in cloud computing
e network, similar to CPU and memory, is a critical and shared resource in the cloud. However, unlike other resources, it is neither shared proportionally to payment, nor do cl...
Lucian Popa 0002, Gautam Kumar, Mosharaf Chowdhury...
IPPS
2002
IEEE
14 years 3 months ago
Dynamic Power Management of Multiprocessor Systems
Power management is critical to power-constrained real-time systems. In this paper, we present a dynamic power management algorithm. Unlike other approaches that focus on the trad...
Jinwoo Suh, Dong-In Kang, Stephen P. Crago
ISCA
2005
IEEE
115views Hardware» more  ISCA 2005»
14 years 4 months ago
RENO - A Rename-Based Instruction Optimizer
RENO is a modified MIPS R10000 register renamer that uses map-table “short-circuiting” to implement dynamic versions of several well-known static optimizations: move eliminat...
Vlad Petric, Tingting Sha, Amir Roth
IPPS
2008
IEEE
14 years 5 months ago
Performance comparison of SGI Altix 4700 and SGI Altix 3700 Bx2
Suitability of the next generation of high-performance computing systems for petascale simulations will depend on a balance between factors such as processor performance, memory p...
Subhash Saini, Dennis C. Jespersen, Dale Talcott, ...