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ISCA
2011
IEEE
238views Hardware» more  ISCA 2011»
12 years 11 months ago
Rebound: scalable checkpointing for coherent shared memory
As we move to large manycores, the hardware-based global checkpointing schemes that have been proposed for small shared-memory machines do not scale. Scalability barriers include ...
Rishi Agarwal, Pranav Garg, Josep Torrellas
ISCA
2011
IEEE
287views Hardware» more  ISCA 2011»
12 years 11 months ago
Scalable power control for many-core architectures running multi-threaded applications
Optimizing the performance of a multi-core microprocessor within a power budget has recently received a lot of attention. However, most existing solutions are centralized and cann...
Kai Ma, Xue Li, Ming Chen, Xiaorui Wang
ISCA
2011
IEEE
522views Hardware» more  ISCA 2011»
12 years 11 months ago
CPPC: correctable parity protected cache
Due to shrinking feature sizes processors are becoming more vulnerable to soft errors. Write-back caches are particularly vulnerable since they hold dirty data that do not exist i...
Mehrtash Manoochehri, Murali Annavaram, Michel Dub...
ISCA
2011
IEEE
290views Hardware» more  ISCA 2011»
12 years 11 months ago
Increasing the effectiveness of directory caches by deactivating coherence for private memory blocks
To meet the demand for more powerful high-performance shared-memory servers, multiprocessor systems must incorporate efficient and scalable cache coherence protocols, such as thos...
Blas Cuesta, Alberto Ros, María Engracia G&...
ASPDAC
2011
ACM
167views Hardware» more  ASPDAC 2011»
12 years 11 months ago
Variation-tolerant and self-repair design methodology for low temperature polycrystalline silicon liquid crystal and organic lig
- In low temperature polycrystalline silicon (LTPS) based display technologies, the electrical parameter variations in thin film transistors (TFTs) caused by random grain boundarie...
Chih-Hsiang Ho, Chao Lu, Debabrata Mohapatra, Kaus...
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