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» Single Run Optimization Using the Reverse-Simulation Method
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117
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AOSD
2008
ACM
15 years 4 months ago
Edicts: implementing features with flexible binding times
In a software product line, the binding time of a feature is the time at which one decides to include or exclude a feature from a product. Typical binding site implementations are...
Venkat Chakravarthy, John Regehr, Eric Eide
125
Voted
SODA
2010
ACM
171views Algorithms» more  SODA 2010»
15 years 12 months ago
Coresets and Sketches for High Dimensional Subspace Approximation Problems
We consider the problem of approximating a set P of n points in Rd by a j-dimensional subspace under the p measure, in which we wish to minimize the sum of p distances from each p...
Dan Feldman, Morteza Monemizadeh, Christian Sohler...
137
Voted
ISCA
2010
IEEE
229views Hardware» more  ISCA 2010»
15 years 29 days ago
Understanding sources of inefficiency in general-purpose chips
Due to their high volume, general-purpose processors, and now chip multiprocessors (CMPs), are much more cost effective than ASICs, but lag significantly in terms of performance a...
Rehan Hameed, Wajahat Qadeer, Megan Wachs, Omid Az...
147
Voted
VLDB
2005
ACM
121views Database» more  VLDB 2005»
15 years 8 months ago
Improving Database Performance on Simultaneous Multithreading Processors
Simultaneous multithreading (SMT) allows multiple threads to supply instructions to the instruction pipeline of a superscalar processor. Because threads share processor resources,...
Jingren Zhou, John Cieslewicz, Kenneth A. Ross, Mi...
124
Voted
CANPC
1999
Springer
15 years 6 months ago
Implementing Application-Specific Cache-Coherence Protocols in Configurable Hardware
Streamlining communication is key to achieving good performance in shared-memory parallel programs. While full hardware support for cache coherence generally offers the best perfo...
David Brooks, Margaret Martonosi