This paper proposes a library-free technology mapping algorithm to reduce delay in combinational circuits. The algorithm reduces the overall number of series transistors through t...
Felipe S. Marques, Leomar S. da Rosa Jr., Renato P...
Dynamic routing can substantially enhance the quality of service for multiprocessor communication, and can provide intelligent adaptation of faulty links during run time. Implemen...
Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. C...
Education in architecture requires access to a broad range of learning materials to develop flexibility and creativity in design. The learning material is compromised of textual an...
Moritz Stefaner, Elisa Dalla Vecchia, Massimiliano...
In this paper we identify the requirements for creating formal descriptions of learning scenarios designed under the European Higher Education Area paradigm, using competences and ...
In this work we present a system for implementing the placement and routing stages in the FPGA cycle of design, into the physical design stage. We start with the ISCAS benchmarks,...