1859 search results - page 75 / 372 » Sketch-based path design |
SODA
2010
ACM
14 years 6 months ago
2010
ACM
The group Steiner problem is a classical network design problem where we are given a graph and a collection of groups of vertices, and want to build a min-cost subgraph that conne...
ICCAD
2005
IEEE
14 years 6 months ago
2005
IEEE
— The flip-chip package gives the highest chip density of any packaging method to support the pad-limited Application-Specific Integrated Circuit (ASIC) designs. In this paper,...
PATMOS
2005
Springer
14 years 2 months ago
2005
Springer
The time taken for a CMOS logic gate output to change after one or more inputs have changed is called the output delay of the gate. A conventional multi-input CMOS gate is designed...
IJFCS
1998
13 years 8 months ago
1998
Directed acyclic graphs (dags) are often used to model circuits. Path lengths in such dags represent circuit delays. In the vertex splitting problem, the objective is to determine...
INFOCOM
2008
IEEE
14 years 3 months ago
2008
IEEE
Abstract—Radio channel quality of real-world wireless networks tends to exhibit both short-term and long-term temporal variations that are in general difficult to model. To maxi...