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ISLPED
2003
ACM
91views Hardware» more  ISLPED 2003»
14 years 3 months ago
Reducing reorder buffer complexity through selective operand caching
Modern superscalar processors implement precise interrupts by using the Reorder Buffer (ROB). In some microarchitectures , such as the Intel P6, the ROB also serves as a repositor...
Gurhan Kucuk, Dmitry Ponomarev, Oguz Ergin, Kanad ...
IPPS
2002
IEEE
14 years 2 months ago
Communication Characteristics of Large-Scale Scientific Applications for Contemporary Cluster Architectures
This paper examines the explicit communication characteristics of several sophisticated scientific applications, which, by themselves, constitute a representative suite of publicl...
Jeffrey S. Vetter, Frank Mueller
ISCA
1999
IEEE
94views Hardware» more  ISCA 1999»
14 years 2 months ago
Storageless Value Prediction Using Prior Register Values
This paper presents a technique called register value prediction (RVP) which uses a type of locality called register-value reuse. By predicting that an instruction will produce th...
Dean M. Tullsen, John S. Seng
IPPS
1998
IEEE
14 years 2 months ago
An Efficient Counting Network
Counting networks were introduced as a new class of concurrent, distributed, low contention data structures suitable for implementing shared counters. Their structure is similar t...
Costas Busch, Marios Mavronicolas
ATAL
2007
Springer
14 years 1 months ago
Reputation in the joint venture game
In many settings, agents need to identify competent partners to assist them in accomplishing tasks. Direct experience may not provide sufficient data to learn the competence of ot...
Philip Hendrix, Barbara J. Grosz