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CASES
2005
ACM
13 years 10 months ago
Architectural support for real-time task scheduling in SMT processors
In Simultaneous Multithreaded (SMT) architectures most hardware resources are shared between threads. This provides a good cost/performance trade-off which renders these architec...
Francisco J. Cazorla, Peter M. W. Knijnenburg, Riz...
CODES
2008
IEEE
14 years 2 months ago
Intra- and inter-processor hybrid performance modeling for MPSoC architectures
The heterogeneity of modern MPSoC architectures, coupled with the increasing complexity of the applications mapped onto them has recently led to a lot of interest in hybrid perfor...
Frank E. B. Ophelders, Samarjit Chakraborty, Henk ...
CASES
2000
ACM
14 years 8 days ago
A code generation framework for Java component-based designs
In this paper, we describe a software architecture supporting code generation from within Ptolemy II. Ptolemy II is a componentbased design tool intended for embedded and real-tim...
Jeff Tsay, Christopher Hylands, Edward Lee
EMSOFT
2004
Springer
14 years 1 months ago
Towards direct execution of esterel programs on reactive processors
Esterel is a system-level language for the modelling, verification and synthesis of control dominated (reactive) embedded systems. Existing Esterel compilers generate intermediat...
Partha S. Roop, Zoran A. Salcic, M. W. Sajeewa Day...
LCTRTS
2001
Springer
14 years 10 days ago
ILP-based Instruction Scheduling for IA-64
The IA-64 architecture has been designed as a synthesis of VLIW and superscalar design principles. It incorporates typical functionality known from embedded processors as multiply...
Daniel Kästner, Sebastian Winkel