Sciweavers

107 search results - page 15 / 22
» Software Cache Coherence for Large Scale Multiprocessors
Sort
View
ISCA
1994
IEEE
129views Hardware» more  ISCA 1994»
13 years 11 months ago
Software Versus Hardware Shared-Memory Implementation: A Case Study
We comparethe performance of software-supported shared memory on a general-purpose network to hardware-supported shared memory on a dedicated interconnect. Up to eight processors,...
Alan L. Cox, Sandhya Dwarkadas, Peter J. Keleher, ...
ISCA
2009
IEEE
199views Hardware» more  ISCA 2009»
14 years 2 months ago
SigRace: signature-based data race detection
Detecting data races in parallel programs is important for both software development and production-run diagnosis. Recently, there have been several proposals for hardware-assiste...
Abdullah Muzahid, Darío Suárez Graci...
IPPS
2009
IEEE
14 years 2 months ago
Scalable RDMA performance in PGAS languages
Partitioned Global Address Space (PGAS) languages provide a unique programming model that can span shared-memory multiprocessor (SMP) architectures, distributed memory machines, o...
Montse Farreras, George Almási, Calin Casca...
MICRO
2007
IEEE
129views Hardware» more  MICRO 2007»
14 years 1 months ago
A Framework for Coarse-Grain Optimizations in the On-Chip Memory Hierarchy
Current on-chip block-centric memory hierarchies exploit access patterns at the fine-grain scale of small blocks. Several recently proposed techniques for coherence traffic reduct...
Jason Zebchuk, Elham Safi, Andreas Moshovos
TC
2011
13 years 2 months ago
Maximizing Spare Utilization by Virtually Reorganizing Faulty Cache Lines
—Aggressive technology scaling to 45nm and below introduces serious reliability challenges to the design of microprocessors. Since a large fraction of chip area is devoted to on-...
Amin Ansari, Shantanu Gupta, Shuguang Feng, Scott ...