This article presents a power estimation tool integrated with an FPGA design flow. It is able to estimate total and individual-node average power consumption for combinational blo...
Elias Todorovich, Fabian Angarita, Javier Valls, E...
The configuration of a computational intelligence (CI) method is responsible for its intelligence (e.g. tolerance, flexibility) as well as its accuracy. In this paper, we investiga...
In this paper, we propose a framework that provides software and robotic agents with the ability to ask approximate questions to each other in the context of heterogeneous ontolog...
Patrick Doherty, Andrzej Szalas, Witold Lukaszewic...
We have recently proposed a general approach to engineering protective wrappers as a means of detecting errors or unwanted behaviour in systems employing an OTS (Off-The-Shelf) ite...
Tom Anderson, Mei Feng, Steve Riddle, Alexander B....
The architecture for a shared memory CPU is described. The CPU allows for parallelism down to the level of single instructions and is tolerant of memory latency. All executable in...