Statistical Power Estimation for FPGA

This article presents a power estimation tool integrated with an FPGA design flow. It is able to estimate total and individual-node average power consumption for combinational blocks. The tool is based on the statistical approach, allowing the user to specify the tolerated error and confidence level of the power estimation. An important feature of this software is the short pulse filtration that leads, in other case, to overestimation. Power maps generation is implemented to help both to detect hot-spots, and perform a power optimization. These maps show the power at every physical position in the die. Several circuits have been tested in order to demonstrate the tool features and usability. The estimated values of dynamic power have been compared with physical measurements for Virtex and Virtex-E devices.

• Type: Conference
• Year: 2005
• Where: FPL
• Authors: Elias Todorovich, Fabian Angarita, Javier Valls, Eduardo I. Boemo
• Keywords: FPL 2005, Individual-node Average Power, Power Estimation, Power Estimation Tool