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DAC
2009
ACM
16 years 4 months ago
Context-sensitive timing analysis of Esterel programs
Traditionally, synchronous languages, such as Esterel, have been compiled into hardware, where timing analysis is relatively easy. When compiled into software ? e.g., into sequent...
Lei Ju, Bach Khoa Huynh, Samarjit Chakraborty, Abh...
145
Voted
EMSOFT
2005
Springer
15 years 9 months ago
Real-time interfaces for interface-based design of real-time systems with fixed priority scheduling
The central idea behind interface-based design is to describe components by a component interface. In contrast to a component description that describes what a component does, a c...
Ernesto Wandeler, Lothar Thiele
138
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EMSOFT
2004
Springer
15 years 9 months ago
Exploiting prescriptive aspects: a design time capability
Aspect oriented programming (AOP), when used well, has many advantages. Aspects are however, programming-time constructs, i.e., they relate to source code. Previously, we develope...
John A. Stankovic, Prashant Nagaraddi, Zhendong Yu...
146
Voted
CODES
2008
IEEE
15 years 5 months ago
Performance debugging of Esterel specifications
Synchronous languages like Esterel have been widely adopted for designing reactive systems in safety-critical domains such as avionics. Specifications written in Esterel are based...
Lei Ju, Bach Khoa Huynh, Abhik Roychoudhury, Samar...
117
Voted
FPL
2005
Springer
98views Hardware» more  FPL 2005»
15 years 9 months ago
Using DSP Blocks For ROM Replacement: A Novel Synthesis Flow
This paper describes a method based on polynomial approximation for transferring ROM resources used in FPGA designs to multiplication and addition operations. The technique can be...
Gareth W. Morris, George A. Constantinides, Peter ...