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AMAST
2004
Springer
14 years 2 months ago
Formal JVM Code Analysis in JavaFAN
JavaFAN uses a Maude rewriting logic specification of the JVM semantics as the basis of a software analysis tool with competitive performance. It supports formal analysis of concu...
Azadeh Farzan, José Meseguer, Grigore Rosu
KBSE
2007
IEEE
14 years 3 months ago
Sequential circuits for program analysis
A number of researchers have proposed the use of Boolean satisfiability solvers for verifying C programs. They encode correctness checks as Boolean formulas using finitization: ...
Fadi A. Zaraket, Adnan Aziz, Sarfraz Khurshid
ISSRE
2006
IEEE
14 years 3 months ago
A Systematic Approach to Generate Inputs to Test UML Design Models
Practical model validation techniques are needed for model driven development (MDD) techniques to succeed. This paper presents an approach to generating inputs to test UML design ...
Trung T. Dinh-Trong, Sudipto Ghosh, Robert B. Fran...
DATE
2010
IEEE
168views Hardware» more  DATE 2010»
14 years 1 months ago
Verifying UML/OCL models using Boolean satisfiability
Abstract--Nowadays, modeling languages like UML are essential in the design of complex software systems and also start to enter the domain of hardware and hardware/software codesig...
Mathias Soeken, Robert Wille, Mirco Kuhlmann, Mart...
ASPDAC
2005
ACM
117views Hardware» more  ASPDAC 2005»
14 years 2 months ago
Dynamic symmetry-breaking for improved Boolean optimization
With impressive progress in Boolean Satisfiability (SAT) solving and several extensions to pseudo-Boolean (PB) constraints, many applications that use SAT, such as highperformanc...
Fadi A. Aloul, Arathi Ramani, Igor L. Markov, Kare...