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SIGARCH
2008
97views more  SIGARCH 2008»
15 years 4 months ago
SP-NUCA: a cost effective dynamic non-uniform cache architecture
1 This paper presents a simple but effective method to reduce on-chip access latency and improve core isolation in CMP Non-Uniform Cache Architectures (NUCA). The paper introduces ...
Javier Merino, Valentin Puente, Pablo Prieto, Jos&...
TC
2010
14 years 11 months ago
A Counter Architecture for Online DVFS Profitability Estimation
Dynamic voltage and frequency scaling (DVFS) is a well known and effective technique for reducing power consumption in modern microprocessors. An important concern though is to est...
Stijn Eyerman, Lieven Eeckhout
DATE
1999
IEEE
115views Hardware» more  DATE 1999»
15 years 9 months ago
EXPRESSION: A Language for Architecture Exploration through Compiler/Simulator Retargetability
We describe EXPRESSION, a language supporting architectural design space exploration for embedded Systems-onChip (SOC) and automatic generation of a retargetable compiler/simulato...
Ashok Halambi, Peter Grun, Vijay Ganesh, Asheesh K...
EUROMICRO
2005
IEEE
15 years 10 months ago
Distribution of a Hierarchical Component in a Non-Connected Environment
This article addresses the utilisation of the componentbased approach for building and executing a distributed application that can offer services over a set of heterogeneous and ...
Didier Hoareau, Yves Mahéo
SIGCOMM
1999
ACM
15 years 8 months ago
An Integrated Congestion Management Architecture for Internet Hosts
This paper presents a novel framework for managing network congestion from an end-to-end perspective. Our work is motivated by several trends in traffic patterns that threaten th...
Hari Balakrishnan, Hariharan Shankar Rahul, Sriniv...