Sciweavers

214 search results - page 32 / 43
» Software Performance Estimation in MPSoC Design
Sort
View
ISCA
2010
IEEE
219views Hardware» more  ISCA 2010»
14 years 17 days ago
Using hardware vulnerability factors to enhance AVF analysis
Fault tolerance is now a primary design constraint for all major microprocessors. One step in determining a processor’s compliance to its failure rate target is measuring the Ar...
Vilas Sridharan, David R. Kaeli
WSC
1997
13 years 8 months ago
Efficient Instruction Cache Simulation and Execution Profiling with a Threaded-Code Interpreter
We present an extension to an existing SPARC V8 instruction set simulator, SimICS, to support accurate profiling of branches and instruction cache misses. SimICS had previously su...
Peter S. Magnusson
IESS
2009
Springer
182views Hardware» more  IESS 2009»
13 years 5 months ago
Modeling Cache Effects at the Transaction Level
Abstract. Embedded system design complexities are growing exponentially. Demand has increased for modeling techniques that can provide both accurate measurements of delay and fast ...
Ardavan Pedram, David Craven, Andreas Gerstlauer
ACMSE
2009
ACM
14 years 2 months ago
A case for compiler-driven superpage allocation
Most modern microprocessor-based systems provide support for superpages both at the hardware and software level. Judicious use of superpages can significantly cut down the number...
Joshua Magee, Apan Qasem
SIGCOMM
2009
ACM
14 years 2 months ago
Cross-layer wireless bit rate adaptation
This paper presents SoftRate, a wireless bit rate adaptation protocol that is responsive to rapidly varying channel conditions. Unlike previous work that uses either frame recepti...
Mythili Vutukuru, Hari Balakrishnan, Kyle Jamieson