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APCSAC
2007
IEEE
14 years 3 months ago
Implicit Transactional Memory in Kilo-Instruction Multiprocessors
Although they have been the main server technology for many years, multiprocessors are undergoing a renaissance due to multi-core chips and the attractive scalability properties of...
Marco Galluzzi, Enrique Vallejo, Adrián Cri...
ISCA
1993
IEEE
153views Hardware» more  ISCA 1993»
14 years 1 months ago
An Adaptive Cache Coherence Protocol Optimized for Migratory Sharing
Parallel programs that use critical sections and are executed on a shared-memory multiprocessor with a writeinvalidate protocol result in invalidation actions that could be elimin...
Per Stenström, Mats Brorsson, Lars Sandberg
ASPLOS
2009
ACM
14 years 9 months ago
RapidMRC: approximating L2 miss rate curves on commodity systems for online optimizations
Miss rate curves (MRCs) are useful in a number of contexts. In our research, online L2 cache MRCs enable us to dynamically identify optimal cache sizes when cache-partitioning a s...
David K. Tam, Reza Azimi, Livio Soares, Michael St...
SCAM
2006
IEEE
14 years 3 months ago
Normalizing Metamorphic Malware Using Term Rewriting
Metamorphic malware — including certain viruses and worms — rewrite their code during propagation. This paper presents a method for normalizing multiple variants of metamorphi...
Andrew Walenstein, Rachit Mathur, Mohamed R. Chouc...
FOSSACS
2006
Springer
14 years 21 days ago
A Logic of Reachable Patterns in Linked Data-Structures
We define a new decidable logic for expressing and checking invariants of programs that manipulate dynamically-allocated objects via pointers and destructive pointer updates. The ...
Greta Yorsh, Alexander Moshe Rabinovich, Mooly Sag...