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EMSOFT
2010
Springer
13 years 8 months ago
Optimal WCET-aware code selection for scratchpad memory
We propose the first polynomial-time code selection algorithm for minimising the worst-case execution time of a nonnested loop executed on a fully pipelined processor that uses sc...
Hui Wu, Jingling Xue, Sridevan Parameswaran
DAC
2011
ACM
12 years 10 months ago
Process-level virtualization for runtime adaptation of embedded software
Modern processor architectures call for software that is highly tuned to an unpredictable operating environment. Processlevel virtualization systems allow existing software to ada...
Kim M. Hazelwood
GLOBECOM
2006
IEEE
14 years 4 months ago
Scalable Layer-2/Layer-3 Multistage Switching Architectures for Software Routers
Abstract— Software routers are becoming an important alternative to proprietary and expensive network devices, because they exploit the economy of scale of the PC market and open...
Andrea Bianco, Jorge M. Finochietto, Giulio Galant...
CODES
2006
IEEE
14 years 4 months ago
Yield prediction for architecture exploration in nanometer technology nodes: : a model and case study for memory organizations
Process variability has a detrimental impact on the performance of memories and other system components, which can lead to parametric yield loss at the system level due to timing ...
Antonis Papanikolaou, T. Grabner, Miguel Miranda, ...
FASE
2005
Springer
14 years 4 months ago
Checking Memory Safety with Blast
Abstract. Blast is an automatic verification tool for checking temporal safety properties of C programs. Given a C program and a temporal safety property, Blast statically proves ...
Dirk Beyer, Thomas A. Henzinger, Ranjit Jhala, Rup...