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FPGA
2007
ACM
185views FPGA» more  FPGA 2007»
14 years 1 months ago
Power-aware FPGA logic synthesis using binary decision diagrams
Power consumption in field programmable gate arrays (FPGAs) has become an important issue as the FPGA market has grown to include mobile platforms. In this work we present a power...
Kevin Oo Tinmaung, David Howland, Russell Tessier
ISCAS
2005
IEEE
155views Hardware» more  ISCAS 2005»
14 years 1 months ago
Hyperblock formation: a power/energy perspective for high performance VLIW architectures
— Architectures based on Very Long Instruction Word (VLIW) processors are an optimal choice in the attempt to obtain high performance levels in mobile devices. The effectiveness ...
Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi,...
SIGMETRICS
2000
ACM
217views Hardware» more  SIGMETRICS 2000»
13 years 7 months ago
Experimenting with an Ad Hoc wireless network on campus: insights and experiences
Ad hoc wireless networks are new communication networks that can be dynamically formed and deformed onthe- y, anytime and anywhere. User data is routed with the help of an ad hoc ...
Chai-Keong Toh, Richard Chen, Minar Delwar, Donald...
SIGSOFT
2007
ACM
14 years 8 months ago
Quantitative verification: models techniques and tools
Automated verification is a technique for establishing if certain properties, usually expressed in temporal logic, hold for a system model. The model can be defined using a high-l...
Marta Z. Kwiatkowska
CC
2012
Springer
250views System Software» more  CC 2012»
12 years 3 months ago
Improving Performance of OpenCL on CPUs
Abstract. Data-parallel languages like OpenCL and CUDA are an important means to exploit the computational power of today’s computing devices. In this paper, we deal with two asp...
Ralf Karrenberg, Sebastian Hack