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IPPS
2006
IEEE
15 years 10 months ago
Design flow for optimizing performance in processor systems with on-chip coarse-grain reconfigurable logic
A design flow for processor platforms with on-chip coarse-grain reconfigurable logic is presented. The reconfigurable logic is realized by a 2-Dimensional Array of Processing Elem...
Michalis D. Galanis, Grigoris Dimitroulakos, Const...
126
Voted
ISCAS
2006
IEEE
119views Hardware» more  ISCAS 2006»
15 years 10 months ago
Performance improvement of the H.264/AVC deblocking filter using SIMD instructions
The H.264/AVC standard defines an in-loop de- instructions, available in current multimedia SIMD instruction blocking filter which is used in both the encoder and decoder. This set...
Stephen Warrington, Hassan Shojania, Subramania Su...
PARA
2004
Springer
15 years 9 months ago
A Family of High-Performance Matrix Multiplication Algorithms
During the last half-decade, a number of research efforts have centered around developing software for generating automatically tuned matrix multiplication kernels. These include ...
John A. Gunnels, Fred G. Gustavson, Greg Henry, Ro...
136
Voted
UIST
1999
ACM
15 years 8 months ago
The Role of Kinesthetic Reference Frames in Two-Handed Input Performance
We present experimental work which explores how the match (or mismatch) between the input space of the hands and the output space of a graphical display influences twohanded input...
Ravin Balakrishnan, Ken Hinckley
IPPS
1999
IEEE
15 years 8 months ago
An Approach for Measuring IP Security Performance in a Distributed Environment
Abstract. The Navy needs to use Multi Level Security (MLS) techniques in an environment with increasing amount of real time computation brought about by increased automation requir...
Brett L. Chappell, David T. Marlow, Philip M. Irey...