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ICCAD
2003
IEEE
175views Hardware» more  ICCAD 2003»
14 years 4 months ago
Path Delay Estimation using Power Supply Transient Signals: A Comparative Study using Fourier and Wavelet Analysis
Transient Signal Analysis (TSA) is a parametric device testing technique based on the analysis of dynamic (transient) current (iDDT) drawn by the core logic from the power supply ...
Abhishek Singh, Jitin Tharian, Jim Plusquellic
ARCS
2010
Springer
14 years 11 days ago
Complexity-Effective Rename Table Design for Rapid Speculation Recovery
Register renaming is a widely used technique to remove false data dependencies in contemporary superscalar microprocessors. The register rename logic includes a mapping table that ...
Görkem Asilioglu, Emine Merve Kaya, Oguz Ergi...
SEFM
2009
IEEE
14 years 2 months ago
Adjusted Verification Rules for Loops Are More Complete and Give Better Diagnostics for Less
—Increasingly, tools and their underlying theories are able to cope with “real code” written as part of industrial grade applications almost as is. It has been our experience...
Patrice Chalin
MICRO
2010
IEEE
172views Hardware» more  MICRO 2010»
13 years 5 months ago
Architectural Support for Fair Reader-Writer Locking
Abstract--Many shared-memory parallel systems use lockbased synchronization mechanisms to provide mutual exclusion or reader-writer access to memory locations. Software locks are i...
Enrique Vallejo, Ramón Beivide, Adriá...
EMSOFT
2007
Springer
14 years 1 months ago
Buffer optimization and dispatching scheme for embedded systems with behavioral transparency
Software components are modular and can enable post-deployment update, but their high overhead in runtime and memory is prohibitive for many embedded systems. This paper proposes ...
Jiwon Hahn, Pai H. Chou