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ICPP
1996
IEEE
13 years 12 months ago
A Timestamp-based Selective Invalidation Scheme for Multiprocessor Cache Coherence
- Among all software cache coherence strategaes, the ones that are based on the concept of tamestamps show the greatest potentaal an terms of cache performance. The early tamestamp...
Xin Yuan, Rami G. Melhem, Rajiv Gupta
WCRE
2009
IEEE
14 years 2 months ago
NTrace: Function Boundary Tracing for Windows on IA-32
—For a long time, dynamic tracing has been an enabling technique for reverse engineering tools. Tracing can not only be used to record the control flow of a particular component...
Johannes Passing, Alexander Schmidt, Martin von L&...
EUROSYS
2011
ACM
12 years 11 months ago
SRM-buffer: an OS buffer management technique to prevent last level cache from thrashing in multicores
Buffer caches in operating systems keep active file blocks in memory to reduce disk accesses. Related studies have been focused on how to minimize buffer misses and the caused pe...
Xiaoning Ding, Kaibo Wang, Xiaodong Zhang
DAC
2003
ACM
14 years 8 months ago
Automatic trace analysis for logic of constraints
Verification of system designs continues to be a major challenge today. Simulation remains the primary tool for making sure that implementations perform as they should. We present...
Xi Chen, Harry Hsieh, Felice Balarin, Yosinori Wat...
CN
2002
89views more  CN 2002»
13 years 7 months ago
Graphic visualization and animation of LOTOS execution traces
Abstract. Two types of visualization and animation tools for LOTOS execution traces are presented: a translator from LOTOS traces to Message Sequence Charts and a graphic animator....
Bernard Stepien, Luigi Logrippo