Sciweavers

596 search results - page 46 / 120
» Software transactional memory for multicore embedded systems
Sort
View
EMSOFT
2007
Springer
14 years 1 months ago
Slice-balancing H.264 video encoding for improved scalability of multicore decoding
With multicore architectures being introduced to the market, the research community is revisiting problems to evaluate them under the new preconditions set by those new systems. A...
Michael Roitzsch
ICECCS
1996
IEEE
109views Hardware» more  ICECCS 1996»
13 years 12 months ago
Dynamically Reconfigurable Embedded Software - Does It Make Sense?
A dynamically reconfigurable real-time software (DRRTS) paradigm can be used effectively in the design of embedded systems to provide many major advantages over conventional softw...
David B. Stewart, Gaurav Arora
EUROSYS
2007
ACM
14 years 4 months ago
Sprint: a middleware for high-performance transaction processing
Sprint is a middleware infrastructure for high performance and high availability data management. It extends the functionality of a standalone in-memory database (IMDB) server to ...
Lásaro J. Camargos, Fernando Pedone, Marcin...
IPPS
2008
IEEE
14 years 2 months ago
Lattice Boltzmann simulation optimization on leading multicore platforms
We present an auto-tuning approach to optimize application performance on emerging multicore architectures. The methodology extends the idea of searchbased performance optimizatio...
Samuel Williams, Jonathan Carter, Leonid Oliker, J...
DATE
2005
IEEE
138views Hardware» more  DATE 2005»
13 years 9 months ago
BB-GC: Basic-Block Level Garbage Collection
Memory space limitation is a serious problem for many embedded systems from diverse application domains. While circuit/packaging techniques are definitely important to squeeze la...
Ozcan Ozturk, Mahmut T. Kandemir, Mary Jane Irwin