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» Software transactional memory for multicore embedded systems
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EMSOFT
2009
Springer
14 years 3 months ago
Adding aggressive error correction to a high-performance compressing flash file system
While NAND flash memories have rapidly increased in both capacity and performance and are increasingly used as a storage device in many embedded systems, their reliability has de...
Yangwook Kang, Ethan L. Miller
CODES
2010
IEEE
13 years 6 months ago
Statistical approach in a system level methodology to deal with process variation
The impact of process variation in state of the art technology makes traditional (worst case) designs unnecessarily pessimistic, which translates to suboptimal designs in terms of...
Concepción Sanz Pineda, Manuel Prieto, Jos&...
ISSS
2002
IEEE
154views Hardware» more  ISSS 2002»
14 years 1 months ago
Optimal Code Size Reduction for Software-Pipelined and Unfolded Loops
Software pipelining and unfolding are commonly used techniques to increase parallelism for DSP applications. However, these techniques expand the code size of the application sign...
Bin Xiao, Zili Shao, Chantana Chantrapornchai, Edw...
CODES
2009
IEEE
14 years 1 months ago
Native MPSoC co-simulation environment for software performance estimation
Performance estimation of Multi-Processor System-On-Chip (MPa high abstraction level is required in order to perform early architecture exploration and accurate design validations...
Patrice Gerin, Mian Muhammad Hamayun, Fréd&...
SCOPES
2005
Springer
14 years 2 months ago
The Bit-reversal SDRAM Address Mapping
The performance contributions of SDRAM address mapping techniques in the main memory of an embedded system are studied and examined. While spatial locality existing in the access ...
Jun Shao, Brian T. Davis