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» Software transactional memory for multicore embedded systems
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CODES
2007
IEEE
14 years 3 months ago
Compile-time decided instruction cache locking using worst-case execution paths
Caches are notorious for their unpredictability. It is difficult or even impossible to predict if a memory access results in a definite cache hit or miss. This unpredictability i...
Heiko Falk, Sascha Plazar, Henrik Theiling
LCTRTS
2007
Springer
14 years 2 months ago
Frequency-aware energy optimization for real-time periodic and aperiodic tasks
Energy efficiency is an important factor in embedded systems design. We consider an embedded system with a dynamic voltage scaling (DVS) capable processor and its system-wide pow...
Xiliang Zhong, Cheng-Zhong Xu
CASES
2010
ACM
13 years 6 months ago
Improved procedure placement for set associative caches
The performance of most embedded systems is critically dependent on the memory hierarchy performance. In particular, higher cache hit rate can provide significant performance boos...
Yun Liang, Tulika Mitra
ICPADS
2006
IEEE
14 years 2 months ago
SPM Conscious Loop Scheduling for Embedded Chip Multiprocessors
One of the major factors that can potentially slow down widespread use of embedded chip multiprocessors is lack of efficient software support. In particular, automated code paral...
Liping Xue, Mahmut T. Kandemir, Guangyu Chen, Tayl...
ICSE
2009
IEEE-ACM
14 years 3 months ago
Deployment automation with BLITZ
Minimizing the computing infrastructure (such as processors) in a distributed real-time embedded (DRE) system deployment helps reduce system size, weight, power consumption, and c...
Brian Dougherty, Jules White, Jaiganesh Balasubram...