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MICRO
2009
IEEE
133views Hardware» more  MICRO 2009»
16 years 13 days ago
A tagless coherence directory
A key challenge in architecting a CMP with many cores is maintaining cache coherence in an efficient manner. Directory-based protocols avoid the bandwidth overhead of snoop-based ...
Jason Zebchuk, Vijayalakshmi Srinivasan, Moinuddin...
HPCC
2005
Springer
15 years 11 months ago
Reducing Memory Sharing Overheads in Distributed JVMs
Distributed JVM systems enable concurrent Java applications to transparently run on clusters of commodity computers by supporting Java’s shared-memory model over multiple JVMs di...
Marcelo Lobosco, Orlando Loques, Claudio Luis de A...
MICRO
2010
IEEE
189views Hardware» more  MICRO 2010»
15 years 3 months ago
A Dynamically Adaptable Hardware Transactional Memory
Most Hardware Transactional Memory (HTM) implementations choose fixed version and conflict management policies at design time. While eager HTM systems store transactional state in-...
Marc Lupon, Grigorios Magklis, Antonio Gonzá...
IEEEPACT
2005
IEEE
15 years 11 months ago
Characterization of TCC on Chip-Multiprocessors
Transactional Coherence and Consistency (TCC) is a novel coherence scheme for shared memory multiprocessors that uses programmer-defined transactions as the fundamental unit of p...
Austen McDonald, JaeWoong Chung, Hassan Chafi, Chi...
229
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ISCA
1997
IEEE
137views Hardware» more  ISCA 1997»
15 years 10 months ago
VM-Based Shared Memory on Low-Latency, Remote-Memory-Access Networks
Recent technological advances have produced network interfaces that provide users with very low-latency access to the memory of remote machines. We examine the impact of such netw...
Leonidas I. Kontothanassis, Galen C. Hunt, Robert ...