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ASPDAC
2006
ACM
134views Hardware» more  ASPDAC 2006»
14 years 1 months ago
Constraint driven I/O planning and placement for chip-package co-design
System-on-chip and system-in-package result in increased number of I/O cells and complicated constraints for both chip designs and package designs. This renders the traditional ma...
Jinjun Xiong, Yiu-Chung Wong, Egino Sarto, Lei He
TCAD
2010
136views more  TCAD 2010»
13 years 2 months ago
Bounded Model Debugging
Design debugging is a major bottleneck in modern VLSI design flows as both the design size and the length of the error trace contribute to its inherent complexity. With typical des...
Brian Keng, Sean Safarpour, Andreas G. Veneris
NIPS
2004
13 years 8 months ago
Hierarchical Eigensolver for Transition Matrices in Spectral Methods
We show how to build hierarchical, reduced-rank representation for large stochastic matrices and use this representation to design an efficient algorithm for computing the largest...
Chakra Chennubhotla, Allan D. Jepson
ICRA
2006
IEEE
225views Robotics» more  ICRA 2006»
14 years 1 months ago
Constraint Optimization Coordination Architecture for Search and Rescue Robotics
— The dangerous and time sensitive nature of a disaster area makes it an ideal application for robotic exploration. Our long term goal is to enable humans, software agents, and a...
Mary Koes, Illah R. Nourbakhsh, Katia P. Sycara
JSA
2007
191views more  JSA 2007»
13 years 7 months ago
Automated memory-aware application distribution for Multi-processor System-on-Chips
Mapping of applications on a Multiprocessor System-on-Chip (MP-SoC) is a crucial step to optimize performance, energy and memory constraints at the same time. The problem is formu...
Heikki Orsila, Tero Kangas, Erno Salminen, Timo D....