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» Solving Over-Constrained Problems with SAT
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ICCAD
2002
IEEE
142views Hardware» more  ICCAD 2002»
14 years 6 months ago
SAT and ATPG: Boolean engines for formal hardware verification
In this survey, we outline basic SAT- and ATPGprocedures as well as their applications in formal hardware verification. We attempt to give the reader a trace trough literature and...
Armin Biere, Wolfgang Kunz
CHARME
2003
Springer
196views Hardware» more  CHARME 2003»
14 years 2 months ago
Analyzing the Intel Itanium Memory Ordering Rules Using Logic Programming and SAT
We present a non-operational approach to specifying and analyzing shared memory consistency models. The method uses higher order logic to capture a complete set of ordering constra...
Yue Yang, Ganesh Gopalakrishnan, Gary Lindstrom, K...
ICTAI
2003
IEEE
14 years 2 months ago
Eliminating Redundancies in SAT Search Trees
Conflict analysis is a powerful paradigm of backtrack search algorithms, in particular for solving satisfiability problems arising from practical applications. Accordingly, most...
Richard Ostrowski, Bertrand Mazure, Lakhdar Sais, ...
CPAIOR
2010
Springer
14 years 1 months ago
A Constraint Integer Programming Approach for Resource-Constrained Project Scheduling
Abstract. We propose a hybrid approach for solving the resource-constrained project scheduling problem which is an extremely hard to solve combinatorial optimization problem of pra...
Timo Berthold, Stefan Heinz, Marco E. Lübbeck...
MTV
2003
IEEE
154views Hardware» more  MTV 2003»
14 years 2 months ago
Tuning the VSIDS Decision Heuristic for Bounded Model Checking
Bounded Model Checking (BMC) techniques have been used for formal hardware verification, with the help of tools such as GRASP (Generic search Algorithm for Satisfiability Proble...
Ohad Shacham, Emmanuel Zarpas