Sciweavers

261 search results - page 8 / 53
» Some Synchronization Issues When Designing Embedded Systems ...
Sort
View
MEMOCODE
2006
IEEE
14 years 1 months ago
Latency-insensitive design and central repetitive scheduling
The theory of latency-insensitive design (LID) was recently invented to cope with the time closure problem in otherwise synchronous circuits and programs. The idea is to allow the...
Julien Boucaron, Robert de Simone, Jean-Vivien Mil...
CCECE
2006
IEEE
14 years 1 months ago
QOS Driven Network-on-Chip Design for Real Time Systems
Real Time embedded system designers are facing extreme challenges in underlying architectural design selection. It involves the selection of a programmable, concurrent, heterogene...
Ankur Agarwal, Mehmet Mustafa, Abhijit S. Pandya
RTAS
2008
IEEE
14 years 1 months ago
Physical Assembly Mapper: A Model-Driven Optimization Tool for QoS-Enabled Component Middleware
This paper provides four contributions to the study of optimization techniques for component-based distributed realtime and embedded (DRE) systems. First, we describe key challeng...
Krishnakumar Balasubramanian, Douglas C. Schmidt
ECRTS
2009
IEEE
13 years 5 months ago
On the Design and Implementation of a Cache-Aware Multicore Real-Time Scheduler
Multicore architectures, which have multiple processing units on a single chip, have been adopted by most chip manufacturers. Most such chips contain on-chip caches that are share...
John M. Calandrino, James H. Anderson
RTCSA
2005
IEEE
14 years 1 months ago
Research Issues in the Development of Context-Aware Middleware Architectures
Context-aware middleware encompasses uniform ions and reliable services for common operations, supports for most of the tasks involved in dealing with context, and thus simplifyin...
Hung Quoc Ngo, Anjum Shehzad, Kim Anh Pham Ngoc, S...