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» Space of DRAM fault models and corresponding testing
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ICCAD
2007
IEEE
110views Hardware» more  ICCAD 2007»
14 years 4 months ago
A hybrid scheme for compacting test responses with unknown values
This paper presents a hybrid compaction scheme for test responses containing unknown values, which consists of a space compactor and an unknown-blocking Multiple Input Signature R...
Mango Chia-Tso Chao, Kwang-Ting Cheng, Seongmoon W...
ICCAD
1995
IEEE
180views Hardware» more  ICCAD 1995»
13 years 11 months ago
Design based analog testing by Characteristic Observation Inference
In this paper, a new approach to analog test design based on the circuit design process, called Characteristic Observation Inference (COI), is presented. In many situations, it is...
Walter M. Lindermeir, Helmut E. Graeb, Kurt Antrei...
ICASSP
2011
IEEE
12 years 11 months ago
Smart grid monitoring for intrusion and fault detection with new locally optimum testing procedures
The vulnerability of smart grid systems is a growing concern. Signal detection theory is employed here to detect a change in the system. We employ a discrete-time linear state spa...
Qian He, Rick S. Blum
AADEBUG
1995
Springer
13 years 11 months ago
Software Testability Measurement for Assertion Placement and Fault Localization
Software testability, the tendency for software to reveal its faults during testing, is an important issue for veri cation and quality assurance. Testability measurement can also b...
Jeffrey M. Voas
DFT
1999
IEEE
119views VLSI» more  DFT 1999»
13 years 11 months ago
RAMSES: A Fast Memory Fault Simulator
In this paper, we present a memory fault simulator called the Random Access Memory Simulator for Error Screening (RAMSES). Although it was designed based on some wellknown memory ...
Chi-Feng Wu, Chih-Tsun Huang, Cheng-Wen Wu