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QEST
2006
IEEE
14 years 3 months ago
Modeling Fiber Delay Loops in an All Optical Switch
We analyze the effect of a few fiber delay loops on the number of deflections in an all optical packet switch. The switch is based on the ROMEO architecture developed by Alcatel...
Ana Busic, Mouad Ben Mamoun, Jean-Michel Fourneau
CSL
2009
Springer
14 years 4 months ago
On the Parameterised Intractability of Monadic Second-Order Logic
One of Courcelle’s celebrated results states that if C is a class of graphs of bounded tree-width, then model-checking for monadic second order logic (MSO2) is fixed-parameter t...
Stephan Kreutzer
RTSS
2008
IEEE
14 years 4 months ago
Symbolic Computation of Schedulability Regions Using Parametric Timed Automata
In this paper, we address the problem of symbolically computing the region in the parameter’s space that guarantees a feasible schedule, given a set of real-time tasks character...
Alessandro Cimatti, Luigi Palopoli, Yusi Ramadian
ECAI
2008
Springer
13 years 11 months ago
Justification-Based Non-Clausal Local Search for SAT
While stochastic local search (SLS) techniques are very efficient in solving hard randomly generated propositional satisfiability (SAT) problem instances, a major challenge is to i...
Matti Järvisalo, Tommi A. Junttila, Ilkka Nie...
DATE
2009
IEEE
90views Hardware» more  DATE 2009»
14 years 4 months ago
Property analysis and design understanding
—Verification is a major issue in circuit and system design. Formal methods like bounded model checking (BMC) can guarantee a high quality of the verification. There are severa...
Ulrich Kühne, Daniel Große, Rolf Drechs...