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HPCA
2007
IEEE
14 years 9 months ago
A Burst Scheduling Access Reordering Mechanism
Utilizing the nonuniform latencies of SDRAM devices, access reordering mechanisms alter the sequence of main memory access streams to reduce the observed access latency. Using a r...
Jun Shao, Brian T. Davis
CGO
2003
IEEE
14 years 26 days ago
METRIC: Tracking Down Inefficiencies in the Memory Hierarchy via Binary Rewriting
In this paper, we present METRIC, an environment for determining memory inefficiencies by examining data traces. METRIC is designed to alter the performance behavior of applicatio...
Jaydeep Marathe, Frank Mueller, Tushar Mohan, Bron...
ISCI
2007
141views more  ISCI 2007»
13 years 9 months ago
A performance comparison of distance-based query algorithms using R-trees in spatial databases
Efficient processing of distance-based queries (DBQs) is of great importance in spatial databases due to the wide area of applications that may address such queries. The most repr...
Antonio Corral, Jesús Manuel Almendros-Jim&...
SCP
2008
144views more  SCP 2008»
13 years 9 months ago
Implicit ownership types for memory management
Abstract. The Real-time Specification for Java (RTSJ) introduced a range of language features for explicit memory management. While the RTSJ gives programmers fine control over mem...
Tian Zhao, Jason Baker, James Hunt, James Noble, J...
SC
2009
ACM
14 years 4 months ago
Increasing memory miss tolerance for SIMD cores
Manycore processors with wide SIMD cores are becoming a popular choice for the next generation of throughput oriented architectures. We introduce a hardware technique called “di...
David Tarjan, Jiayuan Meng, Kevin Skadron