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VLSID
2001
IEEE
129views VLSI» more  VLSID 2001»
14 years 8 months ago
Design Of Provably Correct Storage Arrays
In this paper we describe a hardware design method for memory and register arrays that allows the application of formal equivalence checking for comparing a high-level register tr...
Rajiv V. Joshi, Wei Hwang, Andreas Kuehlmann
CORR
2010
Springer
176views Education» more  CORR 2010»
13 years 7 months ago
Abstraction for Epistemic Model Checking of Dining Cryptographers-based Protocols
ion for Epistemic Model Checking of Dining Cryptographers-based Protocols Omar I. Al-Bataineh and Ron van der Meyden School of Computer Science and Engineering, University of New S...
Omar I. Al-Bataineh, Ron van der Meyden
WWW
2003
ACM
14 years 8 months ago
Engineering the Presentation Layer for Semantic Web Information Systems
This paper presents a design methodology that deals with the presentation aspects involved in the development of a Semantic Web Information System. The methodology is driven by tw...
Flavius Frasincar, Geert-Jan Houben, Peter Barna, ...
SIGSOFT
2007
ACM
14 years 8 months ago
Model checking service compositions under resource constraints
When enacting a web service orchestration defined using the Business Process Execution Language (BPEL) we observed various safety property violations. This surprised us considerab...
David S. Rosenblum, Howard Foster, Jeff Kramer, Je...
ATVA
2008
Springer
144views Hardware» more  ATVA 2008»
13 years 9 months ago
Tests, Proofs and Refinements
1 : Logic in Specification and Verification (abstract) Natarajan Shankar (SRI) Session Chair : Sungdeok Cha 12 : 00 13 : 00 Lunch 13 : 00 15 : 00 2 : Boolean Modeling of Cell Biolo...
Sriram K. Rajamani